[SelectionDAG] Teach computeKnownBits some improvements to ISD::SRL with a non-splat...

[SelectionDAG] Teach computeKnownBits some improvements to ISD::SRL with a non-splat constant shift amount.

If we have a non-splat constant shift amount, the minimum shift amount can be used to infer the number of zero upper bits of the result. There's probably a lot more that we can do here, but this
fixes a case where I wanted to infer the sign bit as zero when all the shift amounts are non-zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319639 91177308-0d34-0410-b5e6-96231b3b80d8