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(parent: b9bf8a1) | patch
target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode
authorPetar Jovanovic <petar.jovanovic@imgtec.com>
Tue, 25 Mar 2014 13:35:18 +0000 (14:35 +0100)
committerAurelien Jarno <aurelien@aurel32.net>
Tue, 25 Mar 2014 22:36:35 +0000 (23:36 +0100)
commit7f6613cedc59fa849105668ae971dc31004bca1c
tree5d9243d510446d94a22d10e44af7c29f38bb16c2tree | snapshot
parentb9bf8a1abb1cafe7184e3dbad9bf8819b3cb620acommit | diff
target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode

Previous implementation presumed that FPU registers are 64-bit and are
working in 64-bit mode. This change first checks MIPS_HFLAG_F64 and if not
set, it does load/store from the odd numbered register pair.
Patch by Matthew Fortune.

Signed-off-by: Matthew Fortune <matthew.fortune@imgtec.com>
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips/translate.c diff | blob | history
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