OSDN Git Service

(root) / android-x86 / external-llvm-project.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 6f56a58) | patch
Add NoMerge MIFlag to avoid MIR branch folding
authorZequan Wu <zequanwu@google.com>
Fri, 29 May 2020 19:15:07 +0000 (12:15 -0700)
committerZequan Wu <zequanwu@google.com>
Fri, 29 May 2020 19:31:06 +0000 (12:31 -0700)
commit80e107ccd088a2705d0e776799a8815a58061cb3
treef697f4807d0544468fbc8a9f219758837ad71d24tree | snapshot
parent6f56a586c505bd587106a9b94388d70efb88155bcommit | diff
Add NoMerge MIFlag to avoid MIR branch folding

Let the codegen recognized the nomerge attribute and disable branch folding when the attribute is given

Differential Revision: https://reviews.llvm.org/D79537
18 files changed:
llvm/include/llvm/CodeGen/MachineInstr.h diff | blob | history
llvm/include/llvm/CodeGen/SelectionDAG.h diff | blob | history
llvm/include/llvm/CodeGen/TargetLowering.h diff | blob | history
llvm/lib/CodeGen/BranchFolding.cpp diff | blob | history
llvm/lib/CodeGen/MIRPrinter.cpp diff | blob | history
llvm/lib/CodeGen/MachineInstr.cpp diff | blob | history
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/lib/Target/ARM/ARMISelLowering.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff | blob | history
llvm/lib/Target/PowerPC/PPCISelLowering.h diff | blob | history
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/nomerge.ll [new file with mode: 0644] blob
llvm/test/CodeGen/ARM/nomerge.ll [new file with mode: 0644] blob
llvm/test/CodeGen/PowerPC/nomerge.ll [new file with mode: 0644] blob
llvm/test/CodeGen/RISCV/nomerge.ll [new file with mode: 0644] blob
llvm/test/CodeGen/X86/nomerge.ll [new file with mode: 0644] blob
external/llvm-project
About OSDN
Find Software
Develop Software
Help