OSDN Git Service

new clock timing design... rtl test env setup ok.
authorastoria-d@fc <astoria-d@fc>
Thu, 11 Aug 2016 09:27:40 +0000 (18:27 +0900)
committerastoria-d@fc <astoria-d@fc>
Thu, 11 Aug 2016 09:27:40 +0000 (18:27 +0900)
commit81a01603b27bf199937b8dd2be27df8f1d3bd93b
treed015a5e33f215bc6935127d22cbeaeaf3a4558b8
parent0937fe7e0780de1b99007f976a75c06af76d3578
new clock timing design... rtl test env setup ok.
de1_nes/cpu/alu.vhd
de1_nes/cpu/mos6502.vhd
de1_nes/mem/prg_rom.vhd
de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
de1_nes/simulation/modelsim/motones_modelsim.mpf