OSDN Git Service

drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 30 Oct 2015 17:21:31 +0000 (19:21 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 10 Nov 2015 14:23:12 +0000 (16:23 +0200)
commit81b088ca87d76d7edacd0f1e3468fd24e6434b2b
tree5b5dc5ecb27460cc36bc89d7afe2ace95b8db04c
parentd2d65408cc8a2368e86bda934f6feafd355e5299
drm/i915: Re-enable PCH FIO underrun reporting after pipe has been disabled

Some hardware (IVB/HSW and CPT/PPT) have a shared error interrupt for
all the relevant underrun bits, so in order to keep the error interrupt
enabled, we need to have underrun reporting enabled on all PCH
transocders. Currently we leave the underrun reporting disabled when
the pipe is off, which means we won't get any underrun interrupts
when only a subset of the pipes are active.

Fix the problem by re-enabling the underrun reporting after the pipe has
been disabled. And to avoid the spurious underruns during pipe enable,
disable the underrun reporting before embarking on the pipe enable
sequence. So this way we have the error reporting disabled while
running through the modeset sequence.

v2: Re-enable PCH FIFO underrun reporting unconditionally on pre-HSW

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v1)
Link: http://patchwork.freedesktop.org/patch/msgid/1446225691-10928-1-git-send-email-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/intel_display.c