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(parent: 500daa0) | patch
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions
authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Wed, 1 Dec 2021 07:32:57 +0000 (16:32 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 7 Dec 2021 15:29:25 +0000 (16:29 +0100)
commit81c1655823237eaec74b2c175ae8e13adfccdaf7
tree63c3032f6854db054d41197566363adc3efd86b6tree | snapshot
parent500daa0e6be292edcf635ba6b090b89da80e90a8commit | diff
dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions

Add all Clock Pulse Generator Core Clock Outputs for the Renesas
R-Car S4-8 (R8A779F0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20211201073308.1003945-4-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
include/dt-bindings/clock/r8a779f0-cpg-mssr.h [new file with mode: 0644] blob
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