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[DAGCombiner] narrow vector binops when extraction is cheap
authorSanjay Patel <spatel@rotateright.com>
Tue, 30 Oct 2018 14:14:34 +0000 (14:14 +0000)
committerSanjay Patel <spatel@rotateright.com>
Tue, 30 Oct 2018 14:14:34 +0000 (14:14 +0000)
commit895148a280193a472fad1431e626a003cd9cf83b
tree3474c3ada107a2229e51c7e62c269a20e1626049
parentd19bba6122bae301c6522dbded9a6065b695c1f5
[DAGCombiner] narrow vector binops when extraction is cheap

Narrowing vector binops came up in the demanded bits discussion in D52912.

I don't think we're going to be able to do this transform in IR as a canonicalization
because of the risk of creating unsupported widths for vector ops, but we already have
a DAG TLI hook to allow what I was hoping for: isExtractSubvectorCheap(). This is
currently enabled for x86, ARM, and AArch64 (although only x86 has existing regression
test diffs).

This is artificially limited to not look through bitcasts because there are so many
test diffs already, but that's marked with a TODO and is a small follow-up.

Differential Revision: https://reviews.llvm.org/D53784

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345602 91177308-0d34-0410-b5e6-96231b3b80d8
24 files changed:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/X86/2012-04-26-sdglue.ll
test/CodeGen/X86/avx-logic.ll
test/CodeGen/X86/avx-vzeroupper.ll
test/CodeGen/X86/avx512-hadd-hsub.ll
test/CodeGen/X86/avx512-insert-extract.ll
test/CodeGen/X86/avx512-skx-insert-subvec.ll
test/CodeGen/X86/known-signbits-vector.ll
test/CodeGen/X86/madd.ll
test/CodeGen/X86/min-legal-vector-width.ll
test/CodeGen/X86/sad.ll
test/CodeGen/X86/shrink_vmul.ll
test/CodeGen/X86/vec_int_to_fp.ll
test/CodeGen/X86/vector-compare-all_of.ll
test/CodeGen/X86/vector-compare-any_of.ll
test/CodeGen/X86/vector-reduce-add.ll
test/CodeGen/X86/vector-reduce-and.ll
test/CodeGen/X86/vector-reduce-fadd-fast.ll
test/CodeGen/X86/vector-reduce-fmul-fast.ll
test/CodeGen/X86/vector-reduce-mul.ll
test/CodeGen/X86/vector-reduce-or.ll
test/CodeGen/X86/vector-reduce-xor.ll
test/CodeGen/X86/vector-rotate-256.ll
test/CodeGen/X86/vector-rotate-512.ll