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RISC-V: Remove EM_RISCV ELF_MACHINE indirection
authorMichael Clark <mjc@sifive.com>
Mon, 5 Mar 2018 07:22:30 +0000 (20:22 +1300)
committerMichael Clark <mjc@sifive.com>
Sat, 5 May 2018 22:39:38 +0000 (10:39 +1200)
commit89854803ce3efb16fbc94604e652f152f5102569
tree8c517efe0a2718ff6ce514d167e2205b8d8a7cfa
parent5b5583806b16ca9ddc454e2a5892b1fea575e470
RISC-V: Remove EM_RISCV ELF_MACHINE indirection

Pointless indirection. Other ports use EM_ constants directly.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
hw/riscv/sifive_e.c
hw/riscv/sifive_u.c
hw/riscv/spike.c
hw/riscv/virt.c
target/riscv/cpu.h