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[TargetLowering] Add SimplifyDemandedBits support for ZERO_EXTEND_VECTOR_INREG
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 13 May 2019 15:51:26 +0000 (15:51 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Mon, 13 May 2019 15:51:26 +0000 (15:51 +0000)
commit89c70147ceb1da23def6979fd2178ca0ac3bb1b2
tree56fa12fce972fdb31119696888f1e77c87275a42
parent0c862149752d942fc16c35d70d0f66b341e3290d
[TargetLowering] Add SimplifyDemandedBits support for ZERO_EXTEND_VECTOR_INREG

More work for PR39709.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360592 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/TargetLowering.cpp
test/CodeGen/X86/vector-reduce-mul-widen.ll
test/CodeGen/X86/vector-reduce-mul.ll