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target/riscv: Use DisasExtend in shift operations
authorRichard Henderson <richard.henderson@linaro.org>
Mon, 23 Aug 2021 19:55:17 +0000 (12:55 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 1 Sep 2021 01:59:12 +0000 (11:59 +1000)
commit89c883091f257d5c2b46f9a5b6ea975b75f41301
tree98e094a9a4d11fd321b0dd246efd9470106d2faf
parent609039150504306a33cd7abf091fd125019bda9d
target/riscv: Use DisasExtend in shift operations

These operations are greatly simplified by ctx->w, which allows
us to fold gen_shiftw into gen_shift.  Split gen_shifti into
gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-13-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvb.c.inc
target/riscv/insn_trans/trans_rvi.c.inc
target/riscv/translate.c