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ARM: handle post-indexed NEON ops where the offset isn't the access width.
authorTim Northover <tnorthover@apple.com>
Thu, 20 Apr 2017 19:54:02 +0000 (19:54 +0000)
committerTim Northover <tnorthover@apple.com>
Thu, 20 Apr 2017 19:54:02 +0000 (19:54 +0000)
commit8cc396e7aaf5c079377227dac1fa292f1509ac0a
treed608df996f87a106d2392533ef716ea83dce1010
parent5078c4cbed56e97eccf205540e47bac20b67ebef
ARM: handle post-indexed NEON ops where the offset isn't the access width.

Before, we assumed that any ConstantInt offset was precisely the access width,
so we could use the "[rN]!" form. ISelLowering only ever created that kind, but
further simplification during combining could lead to unexpected constants and
incorrect codegen.

Should fix PR32658.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300878 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMISelDAGToDAG.cpp
lib/Target/ARM/ARMISelLowering.cpp
test/CodeGen/ARM/alloc-no-stack-realign.ll
test/CodeGen/ARM/memcpy-inline.ll
test/CodeGen/ARM/memset-inline.ll
test/CodeGen/ARM/vector-load.ll
test/CodeGen/ARM/vector-store.ll
test/CodeGen/ARM/vlddup.ll
test/CodeGen/ARM/vldlane.ll
test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll