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(parent: 7c79721) | patch
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
authorPhilippe Mathieu-Daudé <f4bug@amsat.org>
Tue, 1 Dec 2020 11:29:22 +0000 (12:29 +0100)
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>
Thu, 14 Jan 2021 16:13:53 +0000 (17:13 +0100)
commit8cd0b410a24159891809ba5f41fa55abb5adf196
treeeebb4695edc7ab0d6edc156e017b13d75228b09atree | snapshot
parent7c79721606be11b5bc556449e5bcbc331ef6867dcommit | diff
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA

The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-2-f4bug@amsat.org>
target/mips/cpu.h diff | blob | history
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