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[RISCV] Add codegen for RV32F floating point load/store
authorAlex Bradbury <asb@lowrisc.org>
Tue, 20 Mar 2018 13:26:12 +0000 (13:26 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Tue, 20 Mar 2018 13:26:12 +0000 (13:26 +0000)
commit8ce26eb802f4be4f878025a139b686937419147d
tree9f45c73d68861ec27a987c41f302fea4e09e052ctree | snapshot
parent0d055e19c37958f073376c2aecf3aa059592eea2commit | diff
[RISCV] Add codegen for RV32F floating point load/store

As part of this, add support for load/store from the constant pool. This is
used to materialise f32 constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327979 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
lib/Target/RISCV/RISCVISelLowering.h diff | blob | history
lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
lib/Target/RISCV/RISCVInstrInfoF.td diff | blob | history
lib/Target/RISCV/RISCVMCInstLower.cpp diff | blob | history
test/CodeGen/RISCV/float-imm.ll [new file with mode: 0644] blob
test/CodeGen/RISCV/float-mem.ll [new file with mode: 0644] blob
external/llvm
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