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net: hns3: Optimize PF CMDQ interrupt switching process
authorXi Wang <wangxi11@huawei.com>
Wed, 6 Jun 2018 13:07:53 +0000 (14:07 +0100)
committerDavid S. Miller <davem@davemloft.net>
Wed, 6 Jun 2018 18:02:48 +0000 (14:02 -0400)
commit8e52a602b5126183f7a6487c4d48f6a00af4e4fd
treeec2f4b5c77d633b175ebb0f137bd736be6b1757d
parent6444e2a5f1e680278b58ced3568bdff84afe14a5
net: hns3: Optimize PF CMDQ interrupt switching process

When the PF frequently switches the CMDQ interrupt, if the CMDQ_SRC is
not cleared before the hardware interrupt is generated, the new interrupt
will not be reported.

This patch optimizes this problem by clearing CMDQ_SRC and RESET_STS
before enabling interrupt and syncing pending IRQ handlers after disabling
interrupt.

Fixes: 466b0c00391b ("net: hns3: Add support for misc interrupt")
Signed-off-by: Xi Wang <wangxi11@huawei.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c