OSDN Git Service

clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
authorNeil Armstrong <narmstrong@baylibre.com>
Thu, 19 Sep 2019 09:36:26 +0000 (11:36 +0200)
committerJerome Brunet <jbrunet@baylibre.com>
Tue, 1 Oct 2019 12:51:15 +0000 (14:51 +0200)
commit90b171f6035688236a3f09117a683020be45603a
treee95856c905c1e03f5af145a0722a4350c2d61b2c
parent4a079643fc73247667000ba54fbccc2acadb04a5
clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes

When setting the 100MHz, 500MHz, 666MHz and 1GHz rate for CPU clocks,
CCF will use the SYS_PLL to handle these frequencies, but:
- using FIXED_PLL derived FCLK_DIV2/DIV3 clocks is more precise
- the Amlogic G12A/G12B/SM1 Suspend handling in firmware doesn't
  handle entering suspend using SYS_PLL for these frequencies

Adding CLK_MUX_ROUND_CLOSEST on all the muxes of the non-SYS_PLL
cpu clock tree helps CCF always selecting the FCLK_DIV2/DIV3 as source
for these frequencies.

Fixes: ffae8475b90c ("clk: meson: g12a: add notifiers to handle cpu clock change")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
drivers/clk/meson/g12a.c