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target/riscv: Enable native debug itrigger
authorLIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Thu, 13 Oct 2022 06:29:45 +0000 (14:29 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 6 Jan 2023 00:42:55 +0000 (10:42 +1000)
commit91809598a055413d87c10799479086d487558b4e
tree14949985df5aebfd6a7b87f5fc2c878782c49add
parent5a4ae64cac49564354cd6f17598840e4af70e4f5
target/riscv: Enable native debug itrigger

When QEMU is not in icount mode, execute instruction one by one. The
tdata1 can be read directly.

When QEMU is in icount mode, use a timer to simulate the itrigger. The
tdata1 may be not right because of lazy update of count in tdata1. Thus,
We should pack the adjusted count into tdata1 before read it back.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/debug.c