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[X86] Add isel patterns for folding loads when creating ROUND instructions from ffloo...
authorCraig Topper <craig.topper@intel.com>
Tue, 12 Jun 2018 00:48:57 +0000 (00:48 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 12 Jun 2018 00:48:57 +0000 (00:48 +0000)
commit91c6e9af6ed71afb80a15474fb99d8bf016226a8
treeaabebb150d793b454c347a3ed2cebe7d51aa5300
parent8f93b43810b56256d63a1dc7856b8d09aa8cad88
[X86] Add isel patterns for folding loads when creating ROUND instructions from ffloor/fnearbyint/fceil/frint/ftrunc.

We were missing packed isel folding patterns for all of sse41, avx, and avx512.

For some reason avx512 had scalar load folding patterns under optsize(due to partial/undef reg update), but we didn't have the equivalent sse41 and avx patterns.

Sometimes we would get load folding due to peephole pass anyway, but we're also missing avx512 instructions from the load folding table. I'll try to fix that in another patch.

Some of this was spotted in the review for D47993.

This patch adds all the folds to isel, adds a few spot tests, and disables the peephole pass on a few tests to ensure we're testing some of these patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334460 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86InstrAVX512.td
lib/Target/X86/X86InstrSSE.td
test/CodeGen/X86/avx-cvt.ll
test/CodeGen/X86/avx-cvttp2si.ll
test/CodeGen/X86/rounding-ops.ll
test/CodeGen/X86/sse-cvttp2si.ll