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author	Ulrich Weigand <ulrich.weigand@de.ibm.com>
	Fri, 11 Nov 2016 12:48:26 +0000 (12:48 +0000)
committer	Ulrich Weigand <ulrich.weigand@de.ibm.com>
	Fri, 11 Nov 2016 12:48:26 +0000 (12:48 +0000)
commit	93f9010c1f88619dc7da7c95aa760bd921abcf1d
tree	505531a3333b17999f7c62d7c7994f0a55cc07ef	tree \| snapshot
parent	864946f0ea76ed025112565f337959db3af2b8a0	commit \| diff

[SystemZ] Support CL(G)T instructions

This adds support for the compare logical and trap (memory)
instructions that were added as part of the miscellaneous
instruction extensions feature with zEC12.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286587 91177308-0d34-0410-b5e6-96231b3b80d8

external/llvm

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lib/Target/SystemZ/SystemZElimCompare.cpp		diff \| blob \| history
lib/Target/SystemZ/SystemZInstrFormats.td		diff \| blob \| history
lib/Target/SystemZ/SystemZInstrInfo.cpp		diff \| blob \| history
lib/Target/SystemZ/SystemZInstrInfo.td		diff \| blob \| history
lib/Target/SystemZ/SystemZScheduleZ13.td		diff \| blob \| history
lib/Target/SystemZ/SystemZScheduleZEC12.td		diff \| blob \| history
test/CodeGen/SystemZ/trap-02.ll	[new file with mode: 0644]	blob
test/MC/Disassembler/SystemZ/insns.txt		diff \| blob \| history
test/MC/SystemZ/insn-bad-zEC12.s		diff \| blob \| history
test/MC/SystemZ/insn-good-zEC12.s		diff \| blob \| history