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target/arm: Honor HCR_EL2.TID1 trapping requirements
authorMarc Zyngier <maz@kernel.org>
Sun, 1 Dec 2019 12:20:15 +0000 (12:20 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 16 Dec 2019 10:46:34 +0000 (10:46 +0000)
commit93fbc983b29a2eb84e2f6065929caf14f99c3681
treed92702ce78c823872b4fd6cea0b0f1fc82749927
parent630fcd4d2ba37050329e0adafdc552d656ebe2f3
target/arm: Honor HCR_EL2.TID1 trapping requirements

HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1
(and their 32bit equivalents) as well as TCMTR, TLBTR are trapped
to EL2. QEMU ignores it, making it harder for a hypervisor to
virtualize the HW (though to be fair, no known hypervisor actually
cares).

Do the right thing by trapping to EL2 if HCR_EL2.TID1 is set.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-3-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/helper.c