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RISC-V: Add the directive for alignment of stvec's value
authorZong Li <zong@andestech.com>
Thu, 2 Aug 2018 15:21:56 +0000 (23:21 +0800)
committerPalmer Dabbelt <palmer@sifive.com>
Mon, 13 Aug 2018 15:31:31 +0000 (08:31 -0700)
commit94f592f0e5b9c17a7505119a2d6c0f1f529ae93d
tree1756b57cd7fd41d14e9902eba01283caee7d747btree | snapshot
parent62b0194368147def8c5a77ce604a125d620fc582commit | diff
RISC-V: Add the directive for alignment of stvec's value

The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/kernel/head.S diff | blob | history
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