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(parent: 67e45f8) | patch
2002-02-10 Chris Demetriou <cgd@broadcom.com>
authorChris Demetriou <cgd@google.com>
Mon, 11 Feb 2002 06:13:49 +0000 (06:13 +0000)
committerChris Demetriou <cgd@google.com>
Mon, 11 Feb 2002 06:13:49 +0000 (06:13 +0000)
commit9724f27f1c1b2c2098e5f2c92f909c09aaa83199
tree60edbca24f432b695794f4d5dc1ee262dd78f902tree | snapshot
parent67e45f8639c76e10824b865cf12cfed465081aa3commit | diff
2002-02-10  Chris Demetriou  <cgd@broadcom.com>

        * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
        DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
        JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
        SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
        ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
        fields (i.e., add and move commas) so that they more closely
        match the MIPS ISA documentation opcode partitioning.
sim/mips/ChangeLog diff | blob | history
sim/mips/mips.igen diff | blob | history
3.4.x系GCCをフロントエンドとするgnu chains
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