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drm/i915/adlp: Require always a power-of-two sized CCS surface stride
authorImre Deak <imre.deak@intel.com>
Mon, 6 Sep 2021 18:27:11 +0000 (21:27 +0300)
committerImre Deak <imre.deak@intel.com>
Thu, 23 Sep 2021 13:13:26 +0000 (16:13 +0300)
commit9814948e3cfea1771b9f816fb75cae1db4526bd2
treeccd02080378cd30e37fae3f5f6d886406f39456c
parentaad24cc4bd563200e9536b044bdde1550b00103b
drm/i915/adlp: Require always a power-of-two sized CCS surface stride

At the moment CCS FB strides must be power-of-two sized, but a follow-up
change will add support remapping these FBs, allowing the FB passed in
by userspace to have a non-POT sized stride. For these remapped FBs we
can only remap the main surface, not the CCS surface. This means that
userspace has to always generate the CCS surface aligning to the POT
stride padded main surface (by setting up the CCS AUX pagetables
accordingly). Adjust the CCS surface stride check to enforce this.

No functional change.

v2:
- Fix the gen12_ccs_aux_stride() is not static sparse warning.

Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210906182715.3915100-3-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_fb.c