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[X86] Add a DAG combine to turn vzmovl+load into vzload if the load isn't volatile...
authorCraig Topper <craig.topper@intel.com>
Tue, 25 Jun 2019 17:08:26 +0000 (17:08 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 25 Jun 2019 17:08:26 +0000 (17:08 +0000)
commit98b4425f4a26f0461e0b98c84ceb0d592edbd92d
tree9d140aaba950d5574b19dadb98e0f21df3e24e4a
parent6b3b0e03f014e9d9793bada3a12747be80ce75f4
[X86] Add a DAG combine to turn vzmovl+load into vzload if the load isn't volatile. Remove isel patterns for vzmovl+load

We currently have some isel patterns for treating vzmovl+load the same as vzload, but that shrinks the load which we shouldn't do if the load is volatile.

Rather than adding isel checks for volatile. This patch removes the patterns and teachs DAG combine to merge them into vzload when its legal to do so.

Differential Revision: https://reviews.llvm.org/D63665

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364333 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrAVX512.td
lib/Target/X86/X86InstrSSE.td
test/CodeGen/X86/vector-zmov.ll