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(parent: 99d01e0) | patch
clk: aspeed: Add platform driver and register PLLs
authorJoel Stanley <joel@jms.id.au>
Fri, 22 Dec 2017 02:45:20 +0000 (13:15 +1030)
committerStephen Boyd <sboyd@codeaurora.org>
Sat, 27 Jan 2018 00:22:43 +0000 (16:22 -0800)
commit98f3118debb3876399a8da59d72b4908431f1027
treed8ea8be1990e7d1eb05b2602d640090acd786c5dtree | snapshot
parent99d01e0ec3415424210fcd345ebb0c516e4b7fa9commit | diff
clk: aspeed: Add platform driver and register PLLs

This registers a platform driver to set up all of the non-core clocks.

The clocks that have configurable rates are now registered.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-aspeed.c diff | blob | history
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