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(parent: c1f354d) | patch
Have SPU handle halfvec stores aligned by 8 bytes.
authorKalle Raiskila <kalle.raiskila@nokia.com>
Mon, 9 Aug 2010 16:33:00 +0000 (16:33 +0000)
committerKalle Raiskila <kalle.raiskila@nokia.com>
Mon, 9 Aug 2010 16:33:00 +0000 (16:33 +0000)
commit99534bb81a0d945edd61d4db17549bde8449f94c
treefc6921c64831de5654d394a90f4f683aae28bf26tree | snapshot
parentc1f354dcb82e2365a5fd1c39f11199dd2344cfb8commit | diff
Have SPU handle halfvec stores aligned by 8 bytes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/CellSPU/SPUISelLowering.cpp diff | blob | history
lib/Target/CellSPU/SPUISelLowering.h diff | blob | history
lib/Target/CellSPU/SPUInstrInfo.td diff | blob | history
lib/Target/CellSPU/SPUNodes.td diff | blob | history
lib/Target/CellSPU/SPURegisterInfo.cpp diff | blob | history
test/CodeGen/CellSPU/bigstack.ll diff | blob | history
test/CodeGen/CellSPU/v2f32.ll diff | blob | history
external/llvm
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