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(parent: a9e3d2c) | patch
Relaxed memory barriers for x86
authorRazvan A Lupusoru <razvan.a.lupusoru@intel.com>
Wed, 26 Feb 2014 01:41:08 +0000 (17:41 -0800)
committerIan Rogers <irogers@google.com>
Wed, 26 Mar 2014 23:20:09 +0000 (16:20 -0700)
commit99ad7230ccaace93bf323dea9790f35fe991a4a2
tree095705c674703953bf4c50f6a30a105420b770b5tree | snapshot
parenta9e3d2ccfdbf7f4c7b1508bcb2b774037399b1d4commit | diff
Relaxed memory barriers for x86

X86 provides stronger memory guarantees and thus the memory barriers can be
optimized. This patch ensures that all memory barriers for x86 are treated
as scheduling barriers. And in cases where a barrier is needed (StoreLoad case),
an mfence is used.

Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
14 files changed:
compiler/dex/compiler_enums.h diff | blob | history
compiler/dex/quick/arm/int_arm.cc diff | blob | history
compiler/dex/quick/gen_common.cc diff | blob | history
compiler/dex/quick/gen_invoke.cc diff | blob | history
compiler/dex/quick/local_optimizations.cc diff | blob | history
compiler/dex/quick/mir_to_lir-inl.h diff | blob | history
compiler/dex/quick/mir_to_lir.cc diff | blob | history
compiler/dex/quick/mir_to_lir.h diff | blob | history
compiler/dex/quick/x86/assemble_x86.cc diff | blob | history
compiler/dex/quick/x86/codegen_x86.h diff | blob | history
compiler/dex/quick/x86/int_x86.cc diff | blob | history
compiler/dex/quick/x86/target_x86.cc diff | blob | history
compiler/dex/quick/x86/x86_lir.h diff | blob | history
disassembler/disassembler_x86.cc diff | blob | history
art
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