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drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1
authorVivek Kasireddy <vivek.kasireddy@intel.com>
Wed, 17 Jul 2019 02:13:16 +0000 (19:13 -0700)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 18 Jul 2019 17:26:44 +0000 (20:26 +0300)
commit9a36a6517d5cc8bf7d9c1fde9058269701802e31
treecbcc9ec9fbc117225f1ae4d8900cd526a13a712d
parent5270130db8c8694f7d97cc4fdc9440fb30bc2192
drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1

Although, DPLL4 enable and disable is associated with MGPLL1_ENABLE
register, we can use ICL_DPLL_CFGCR0/CR1 macros to access this dpll's
CR0 and CR1 registers by passing an id of 4 to these macros.

Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717021316.18610-1-vivek.kasireddy@intel.com
drivers/gpu/drm/i915/display/intel_dpll_mgr.c