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ibmvnic: Ensure that device queue memory is cache-line aligned
authorDwip N. Banerjee <dnbanerg@us.ibm.com>
Thu, 19 Nov 2020 01:12:22 +0000 (19:12 -0600)
committerJakub Kicinski <kuba@kernel.org>
Sat, 21 Nov 2020 03:50:34 +0000 (19:50 -0800)
commit9a87c3fca2372af3177cb454c7aa381c7080307f
tree8d0b50e08a3b90fc46f2530ecaaa9c7ac19518f8
parent8ed589f3832a0aee3438bee2820fa90b33b40c24
ibmvnic: Ensure that device queue memory is cache-line aligned

PCI bus slowdowns were observed on IBM VNIC devices as a result
of partial cache line writes and non-cache aligned full cache line writes.
Ensure that packet data buffers are cache-line aligned to avoid these
slowdowns.

Signed-off-by: Dwip N. Banerjee <dnbanerg@us.ibm.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/ibm/ibmvnic.c
drivers/net/ethernet/ibm/ibmvnic.h