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[RISCV][MC] Fix nf encoding for vector ld/st whole register
authorShihPo Hung <shihpo.hung@sifive.com>
Tue, 30 Mar 2021 21:30:15 +0000 (14:30 -0700)
committerTom Stellard <tstellar@redhat.com>
Tue, 30 Mar 2021 21:30:15 +0000 (14:30 -0700)
commit9ae9ab1ca34384e07b751c16645e22a0b953b08b
treeb6329438b574cac1b5fbc1badf470cfd83c551d5tree | snapshot
parentff2cf8fafa5ad9a76e59fa086d969d4e2ecc3a39commit | diff
[RISCV][MC] Fix nf encoding for vector ld/st whole register

The three bit nf is one less than the number of NFIELDS,
so we manually decrement 1 for VS1/2/4/8R & VL1/2/4/8R.

Differential revision: https://reviews.llvm.org/D98185

(cherry picked from commit rG5cdb2e98608bf57c216ee7067e8a12d070c9e2bd)
llvm/lib/Target/RISCV/RISCVInstrInfoV.td diff | blob | history
llvm/test/MC/RISCV/rvv/aliases.s diff | blob | history
llvm/test/MC/RISCV/rvv/load.s diff | blob | history
llvm/test/MC/RISCV/rvv/store.s diff | blob | history
external/llvm-project
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