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drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
authorDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Wed, 2 Nov 2016 20:13:21 +0000 (13:13 -0700)
committerJani Nikula <jani.nikula@intel.com>
Fri, 4 Nov 2016 15:42:17 +0000 (17:42 +0200)
commit9c7540241885838cfc7fa58c4a8bd75be0303ed1
tree88830d6ffafec646adb5bee7589e4df7b88a7ee2
parentb30ce9e0552aa017ac6f2243f3c2d8e36fe52e69
drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms

According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
cycling on/off.

Let's apply this work around to GEN9 platforms too, as it fixes the same
issue.

v2: Move drm_device to drm_i915_private conversion

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
Cc: stable@vger.kernel.org
Cc: Libin Yang <libin.yang@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1478117601-19122-1-git-send-email-dhinakaran.pandiyan@intel.com
drivers/gpu/drm/i915/intel_display.c