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(parent: 824af37) | patch
spi-nor: intel-spi: Fix number of protected range registers for BYT/LPT
authorBin Meng <bmeng.cn@gmail.com>
Mon, 11 Sep 2017 09:41:51 +0000 (02:41 -0700)
committerCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Wed, 11 Oct 2017 07:40:06 +0000 (09:40 +0200)
commit9cbb035cc111f5c6655f1026d4e7918282f6e137
tree9f25b6b08e07576d07043be7ec832bfeb6809b9atree | snapshot
parent824af37ef2d054d1f89bd2b9125755a4acc37332commit | diff
spi-nor: intel-spi: Fix number of protected range registers for BYT/LPT

The number of protected range registers is not the same on BYT/LPT/
BXT. GPR0 only exists on Apollo Lake and its offset is reserved on
other platforms.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
drivers/mtd/spi-nor/intel-spi.c diff | blob | history
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