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drm/i915/tgl: simplify the lrc register list for !RCS
authorDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Wed, 9 Oct 2019 23:04:24 +0000 (16:04 -0700)
committerChris Wilson <chris@chris-wilson.co.uk>
Thu, 10 Oct 2019 09:14:42 +0000 (10:14 +0100)
commit9d41318c4e43da6b4c95a21cf366bf18179291fd
treee5443de08e2d47f317c15d5839c3f254e9fe4f95
parentba2c74da52eba388d959a1000a9dd08fa4857659
drm/i915/tgl: simplify the lrc register list for !RCS

There are small differences between the blitter and the video engines in
the xcs context image (e.g. registers 0x200 and 0x204 only exist on the
blitter). Since we never explicitly set a value for those register and
given that we don't need to update the offsets in the lrc image when we
change engine within the class for virtual engine because the HW can
handle that, instead of having a separate define for the BCS we can
just restrict the programming to the part we're interested in, which is
common across the engines.

Bspec: 45584
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191009230424.6507-2-daniele.ceraolospurio@intel.com
drivers/gpu/drm/i915/gt/intel_lrc.c