Quick compiler, MIPS resource cleanup

Quick compiler, MIPS resource cleanup

MIPS architecture includes internal registers HI and LO.
Similar to condition codes in other architectures, these internal
resouces must be accounted for during instruction scheduling.

Previously, the Quick backend for MIPS dealt with them by defining
rHI and rLO pseudo registers - treating them as actual registers for
def/use masks.  This CL changes the handling of these resources to
be in line with how condition codes are used elsewhere - leaving
register definitions to be used for registers.

Change-Id: Idcd77f3107b0c9b081ad05b1aab663fb9f41492d