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clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider
authorChen-Yu Tsai <wens@csie.org>
Thu, 12 Oct 2017 08:36:57 +0000 (16:36 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 25 Dec 2017 13:26:24 +0000 (14:26 +0100)
commit9fe2989cdf3d433ab07d9e5979c5a811e26dd925
treeb616cc84d80390031b6a6157effe52f3cd2cc405
parenta7455b113feff0b99cad533c63bc6b877c1a1960
clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider

[ Upstream commit d51fe3ba9773c8b6fc79f82bbe75d64baf604292 ]

The post-divider for the audio PLL is in bits [29:26], as specified
in the user manual, not [19:16] as currently programmed in the code.
The post-divider has a default register value of 2, i.e. a divider
of 3. This means the clock rate fed to the audio codec would be off.

This was discovered when porting sigma-delta modulation for the PLL
to sun5i, which needs the post-divider to be 1.

Fix the bit offset, so we do actually force the post-divider to a
certain value.

Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/sunxi-ng/ccu-sun5i.c