OSDN Git Service

Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core
authorTaylor Simpson <tsimpson@quicinc.com>
Wed, 17 Mar 2021 16:48:57 +0000 (11:48 -0500)
committerTaylor Simpson <tsimpson@quicinc.com>
Wed, 3 Nov 2021 21:01:26 +0000 (16:01 -0500)
commita1559537d183bf1f4e2cfef972610c8c9e1a6aa5
tree9e4f7493e67621802ca4d0d1395f4ce7010f9ac5
parent375bcf389f1e5f8c3bde70b3f8c847fdd73074c0
Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core

HVX is a set of wide vector instructions.  Machine state includes
    vector registers (VRegs)
    vector predicate registers (QRegs)
    temporary registers for intermediate values
    store buffer (masked stores and scatter/gather)

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
target/hexagon/cpu.c
target/hexagon/cpu.h
target/hexagon/hex_arch_types.h
target/hexagon/insn.h
target/hexagon/internal.h
target/hexagon/mmvec/mmvec.h [new file with mode: 0644]