OSDN Git Service

target/riscv/cpu.c: restrict 'mimpid' value
authorDaniel Henrique Barboza <dbarboza@ventanamicro.com>
Thu, 6 Jul 2023 10:17:22 +0000 (07:17 -0300)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 10 Jul 2023 12:29:15 +0000 (22:29 +1000)
commita1863ad368d32b53153bf417a83f01c85bb9d82c
tree7f2c46f0cf93b454f61da768ca5c3fcb40a36bb5
parent1e341500459e0900a07b0c3a86de4526ebe4496d
target/riscv/cpu.c: restrict 'mimpid' value

Following the same logic used with 'mvendorid' let's also restrict
'mimpid' for named CPUs. Generic CPUs keep setting the value freely.

Note that we're getting rid of the default RISCV_CPU_MARCHID value. The
reason is that this is not a good default since it's dynamic, changing
with with every QEMU version, regardless of whether the actual
implementation of the CPU changed from one QEMU version to the other.
Named CPU should set it to a meaningful value instead and generic CPUs
can set whatever they want.

This is the error thrown for an invalid 'mimpid' value for the veyron-v1
CPU:

$ ./qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mimpid=2
qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mimpid=2:
    Unable to change veyron-v1-riscv-cpu mimpid (0x111)

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230706101738.460804-5-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c