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(parent: b20570e) | patch
ARM: make sure FastISel bails on f64 operations for Cortex-M4.
authorTim Northover <tnorthover@apple.com>
Thu, 23 Feb 2017 22:35:00 +0000 (22:35 +0000)
committerTim Northover <tnorthover@apple.com>
Thu, 23 Feb 2017 22:35:00 +0000 (22:35 +0000)
commita328146a758bf6d3f25429113bfee0a6575be284
tree77b06fb925846218d545d35e4de73253e9b834bftree | snapshot
parentb20570e64734b73fce02d5e4fd3a400c6015d7dacommit | diff
ARM: make sure FastISel bails on f64 operations for Cortex-M4.

FastISel wasn't checking the isFPOnlySP subtarget feature before emitting
double-precision operations, so it got completely invalid CodeGen for doubles
on Cortex-M4F.

The normal ISel testing wasn't spectacular either so I added a second RUN line
to improve that while I was in the area.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296031 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMFastISel.cpp diff | blob | history
test/CodeGen/ARM/fp-only-sp.ll [new file with mode: 0644] blob
external/llvm
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