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GlobalISel: Remove unsigned variant of SrcOp
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 24 Jun 2019 16:16:12 +0000 (16:16 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 24 Jun 2019 16:16:12 +0000 (16:16 +0000)
commita3af6bb71d97a509453dc7c37784b6c8f34f58e6
treebffdc0a37ae8a01a0f57f6bdca0fd9b2ef5070d4
parenta2b05bc24df5456bb21409839677dc86f746b17f
GlobalISel: Remove unsigned variant of SrcOp

Force using Register.

One downside is the generated register enums require explicit
conversion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364194 91177308-0d34-0410-b5e6-96231b3b80d8
28 files changed:
include/llvm/CodeGen/CallingConvLower.h
include/llvm/CodeGen/GlobalISel/CallLowering.h
include/llvm/CodeGen/GlobalISel/CombinerHelper.h
include/llvm/CodeGen/GlobalISel/IRTranslator.h
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
include/llvm/CodeGen/MachineInstrBuilder.h
include/llvm/CodeGen/SwiftErrorValueTracking.h
lib/CodeGen/GlobalISel/CallLowering.cpp
lib/CodeGen/GlobalISel/CombinerHelper.cpp
lib/CodeGen/GlobalISel/IRTranslator.cpp
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
lib/CodeGen/SwiftErrorValueTracking.cpp
lib/Target/AArch64/AArch64CallLowering.cpp
lib/Target/AArch64/AArch64InstructionSelector.cpp
lib/Target/AMDGPU/AMDGPUCallLowering.cpp
lib/Target/AMDGPU/AMDGPUCallLowering.h
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
lib/Target/ARM/ARMCallLowering.cpp
lib/Target/ARM/ARMLegalizerInfo.cpp
lib/Target/Mips/MipsCallLowering.cpp
lib/Target/Mips/MipsCallLowering.h
lib/Target/Mips/MipsInstructionSelector.cpp
lib/Target/Mips/MipsMachineFunction.cpp
lib/Target/Mips/MipsMachineFunction.h
lib/Target/X86/X86CallLowering.cpp
lib/Target/X86/X86RegisterInfo.h
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp