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target/riscv: debug: Determine the trigger type from tdata1.type
authorFrank Chang <frank.chang@sifive.com>
Fri, 9 Sep 2022 13:42:08 +0000 (21:42 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 27 Sep 2022 01:23:57 +0000 (11:23 +1000)
commita42bd0016654cafd6ca8ca4dbb82fc921ca19ae4
tree637dbc5da959eb928ac21a0b4a9445c6b16f9cc1
parent9dfa6c2aec299fda9946c327e889087365a715b5
target/riscv: debug: Determine the trigger type from tdata1.type

Current RISC-V debug assumes that only type 2 trigger is supported.
To allow more types of triggers to be supported in the future
(e.g. type 6 trigger, which is similar to type 2 trigger with additional
 functionality), we should determine the trigger type from tdata1.type.

RV_MAX_TRIGGERS is also introduced in replacement of TRIGGER_TYPE2_NUM.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
[bmeng: fixed MXL_RV128 case, and moved macros to the following patch]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220909134215.1843865-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/csr.c
target/riscv/debug.c
target/riscv/debug.h
target/riscv/machine.c