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drm/i915: Add support for FBs requiring a POT stride alignment
authorImre Deak <imre.deak@intel.com>
Thu, 25 Mar 2021 21:48:06 +0000 (23:48 +0200)
committerImre Deak <imre.deak@intel.com>
Mon, 29 Mar 2021 19:58:12 +0000 (22:58 +0300)
commita4606d4595fd1cb662e4f7a63ac0c04396a0f124
tree21e0cf432ee16e4abcc27d522a40d13d05aeb73f
parent6d80f4308605e1b572777dc19f0297657ec0c206
drm/i915: Add support for FBs requiring a POT stride alignment

An upcoming platform has a restriction that the FB stride must be
power-of-two aligned. To support framebuffer layouts that are not in
this layout add a logic that pads the tile rows to the POT aligned size.

The HW won't read the padding PTEs, so these don't have to point to an
allocated address, or even have their valid flag set. So use a NULL PTE
instead for instance the scratch page, which is simple and keeps the SG
table compact.

v2:
- Simplify plane_view_dst_stride(). (Ville)
- Pass pitch_tiles as unsigned int.
v3:
- Drop unintentional s/plane_state->rotation/plane_config->rotation/
  change.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210325214808.2071517-24-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_display_types.h
drivers/gpu/drm/i915/display/intel_fb.c
drivers/gpu/drm/i915/gt/intel_ggtt.c
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_vma_types.h
drivers/gpu/drm/i915/selftests/i915_vma.c