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[AArch64] LSE Atomics reorg - part 1
authorJoel Jones <joelkevinjones@gmail.com>
Sat, 5 Aug 2017 04:30:55 +0000 (04:30 +0000)
committerJoel Jones <joelkevinjones@gmail.com>
Sat, 5 Aug 2017 04:30:55 +0000 (04:30 +0000)
commita4861e0c2b35948a206ebf150403704b718395ee
tree3ad51d1c40fe3530dbeca42b586f67b561931e07
parentd2f3f4a06ac5ae96f421684a350756e20289797b
[AArch64] LSE Atomics reorg - part 1

Add memory synchronization semantics to LSE Atomics.

The memory semantics feature will be added in a subsequent patch.

In this patch, several corrections were added to the existing LSE Atomics
implementation, based on the ARM Errata D11904 from 05/12/2017.

Patch by: steleman

Differential Revision: https://reviews.llvm.org/D35319

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310167 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/Target/TargetSelectionDAG.td
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
lib/Target/AArch64/AArch64InstrAtomics.td
lib/Target/AArch64/AArch64InstrFormats.td
lib/Target/AArch64/AArch64SchedThunderX2T99.td
test/CodeGen/AArch64/atomic-ops-lse.ll