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ARM: dts: msm: Enable ACD functionality for sdm630 CPU rails
authorTirupathi Reddy <tirupath@codeaurora.org>
Thu, 4 May 2017 17:22:34 +0000 (22:52 +0530)
committerTirupathi Reddy <tirupath@codeaurora.org>
Tue, 11 Jul 2017 04:24:14 +0000 (09:54 +0530)
commita4ca7944f48010708a71ce1fea44d37b53e659e2
tree4d58ef6485abf787d025d21f4a3489c98662bf1e
parentd6f171ce52ce47aa18c80145298c9237fb577e24
ARM: dts: msm: Enable ACD functionality for sdm630 CPU rails

The adaptive clock distribution (ACD) mitigates the impact of
high-frequency supply voltage (VDD) droops on microprocessor
performance. Program ACD functional configuration for both
Silver and Gold clusters of sdm630.

Also set VCTL_RAMP_EN & VCTL_RAMP_EN to 1 in SAW4_AVS_CTL.

CRs-Fixed: 2074210
Change-Id: I1f8021b8b436602b22a87d2036aebbfcf6840f58
Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
arch/arm/boot/dts/qcom/sdm630-pm.dtsi
arch/arm/boot/dts/qcom/sdm630.dtsi