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[AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic
authorTim Renouf <tpr.llvm@botech.co.uk>
Mon, 18 Mar 2019 19:35:44 +0000 (19:35 +0000)
committerTim Renouf <tpr.llvm@botech.co.uk>
Mon, 18 Mar 2019 19:35:44 +0000 (19:35 +0000)
commita90929573cca4829774944334f084d35008ab756
tree982430fdd4e054ea54ef54743724bf14ed5ed516
parent0b9f636469b75cfaa87a9251c4ecfea18717dedc
[AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic

Allow the clamp modifier on vop3 int arithmetic instructions in assembly
and disassembly.

This involved adding a clamp operand to the affected instructions in MIR
and MC, and thus having to fix up several places in codegen and MIR
tests.

Differential Revision: https://reviews.llvm.org/D59267

Change-Id: Ic7775105f02a985b668fa658a0cd7837846a534e

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356399 91177308-0d34-0410-b5e6-96231b3b80d8
23 files changed:
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
lib/Target/AMDGPU/SIInstrInfo.cpp
lib/Target/AMDGPU/SIInstrInfo.td
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
lib/Target/AMDGPU/SIRegisterInfo.cpp
lib/Target/AMDGPU/VOP2Instructions.td
test/CodeGen/AMDGPU/endpgm-dce.mir
test/CodeGen/AMDGPU/fold-immediate-operand-shrink-with-carry.mir
test/CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
test/CodeGen/AMDGPU/global-load-store-atomics.mir
test/CodeGen/AMDGPU/inserted-wait-states.mir
test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
test/CodeGen/AMDGPU/sdwa-ops.mir
test/CodeGen/AMDGPU/shrink-carry.mir
test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
test/MC/AMDGPU/vop3-gfx9.s
test/MC/AMDGPU/vop3.s
test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
test/MC/Disassembler/AMDGPU/vop3_vi.txt