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R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI
authorMarek Olsak <marek.olsak@amd.com>
Tue, 3 Feb 2015 17:38:12 +0000 (17:38 +0000)
committerMarek Olsak <marek.olsak@amd.com>
Tue, 3 Feb 2015 17:38:12 +0000 (17:38 +0000)
commita95296a86e7922cb15058c7c3cb0a6fc6eefb349
tree4a6d84ddf90e07a6907e4acdc510e4c866a110e2
parent2ea95bd4719341e0eb00d79f66ac1fc2e0e3169d
R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI

This can happen when a REV instruction is commuted.

The trick is not to define the _vi versions of instructions, which has these
consequences:
- code generation will always fail if a pseudo cannot be lowered
  (very useful to catch bugs where an unsupported instruction somehow makes
   it to the printer)
- ability to query if a pseudo can be lowered, which is done in commuteOpcode
  to prevent REV from commuting to non-REV on VI

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227990 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/SIInstrInfo.cpp
lib/Target/R600/SIInstrInfo.td
lib/Target/R600/SIInstructions.td
test/CodeGen/R600/shl.ll
test/CodeGen/R600/sra.ll