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(parent: 3f4e349) | patch
drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 23 May 2014 15:30:19 +0000 (21:00 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 11 Jun 2014 14:57:28 +0000 (16:57 +0200)
commitab53c267f28f1830c660aad1a8cc063b34fa1cc2
treedf935cc907c7113fbdfff86d90b51eb0e5be46b0tree | snapshot
parent3f4e349587cd840f01bd24ab6911bbcc790f2b0acommit | diff
drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

CHV uses the gen8 shadow register mechanism so we shouldn't be
checking the GT FIFO status.

This effectively removes the posting read, so add an explicit
posting read using FORCEWAKE_ACK_VLV (which is what use in
vlv_forcewake_reset()).

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_uncore.c diff | blob | history
This is a test repository.
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