[X86] Optimize vector shifts with variable but uniform shift amounts

[X86] Optimize vector shifts with variable but uniform shift amounts

Summary:
For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register.
The lower 64-bits of the register are evaluated to determine the shift amount.
This patch improves the construction of the vector containing the shift amount.

Reviewers: craig.topper, delena, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28353

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291120 91177308-0d34-0410-b5e6-96231b3b80d8