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(parent: 57c8a48) | patch
drm/i915/gvt: Add new 64K entry type
authorChangbin Du <changbin.du@intel.com>
Tue, 15 May 2018 02:35:33 +0000 (10:35 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Mon, 9 Jul 2018 02:22:30 +0000 (10:22 +0800)
commitb294657d1bab3371bf02c31a243232bfa9f4629f
treea46d75f1597acd5499d81ab343ab511d1908ee3atree | snapshot
parent57c8a484a9cbf1315b5299702d12aef04867eeeecommit | diff
drm/i915/gvt: Add new 64K entry type

Add a new entry type GTT_TYPE_PPGTT_PTE_64K_ENTRY. 64K entry is very
different from 2M/1G entry. 64K entry is controlled by IPS bit in upper
PDE. To leverage the current logic, I take IPS bit as 'PSE' for PTE
level. Which means, 64K entries can also processed by get_pse_type().

v2: Make it bisectable.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/gtt.c diff | blob | history
drivers/gpu/drm/i915/gvt/gtt.h diff | blob | history
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