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perf/x86/lbr: Add interface to get LBR information
authorLike Xu <like.xu@linux.intel.com>
Sat, 13 Jun 2020 08:09:48 +0000 (16:09 +0800)
committerPeter Zijlstra <peterz@infradead.org>
Thu, 2 Jul 2020 13:51:46 +0000 (15:51 +0200)
commitb2d6504761a50b9493eb4b20f6e188b673f20c32
tree32db6c3766c09fcb0a371e5a6a71737fc92dc155
parent027440b5d426a51f33b515bbd236cc479d1e051f
perf/x86/lbr: Add interface to get LBR information

The LBR records msrs are model specific. The perf subsystem has already
obtained the base addresses of LBR records based on the cpu model.

Therefore, an interface is added to allow callers outside the perf
subsystem to obtain these LBR information. It's useful for hypervisors
to emulate the LBR feature for guests with less code.

Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200613080958.132489-4-like.xu@linux.intel.com
arch/x86/events/intel/lbr.c
arch/x86/include/asm/perf_event.h