OSDN Git Service

Improve handling of stack accesses in Thumb-1
authorRenato Golin <renato.golin@linaro.org>
Wed, 25 Feb 2015 14:41:06 +0000 (14:41 +0000)
committerRenato Golin <renato.golin@linaro.org>
Wed, 25 Feb 2015 14:41:06 +0000 (14:41 +0000)
commitb451f4e37699b91e33a0a0db66172d2e1ac373f4
tree18a863822035c285902e819da5dc4b1495c524e9
parent3cecbeccf2ecfc1511fec99f0cd7ee5fcad94266
Improve handling of stack accesses in Thumb-1

Thumb-1 only allows SP-based LDR and STR to be word-sized, and SP-base LDR,
STR, and ADD only allow offsets that are a multiple of 4. Make some changes
to better make use of these instructions:

* Use word loads for anyext byte and halfword loads from the stack.
* Enforce 4-byte alignment on objects accessed in this way, to ensure that
  the offset is valid.
* Do the same for objects whose frame index is used, in order to avoid having
  to use more than one ADD to generate the frame index.
* Correct how many bits of offset we think AddrModeT1_s has.

Patch by John Brawn.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230496 91177308-0d34-0410-b5e6-96231b3b80d8
13 files changed:
lib/Target/ARM/ARMBaseRegisterInfo.cpp
lib/Target/ARM/ARMISelDAGToDAG.cpp
lib/Target/ARM/ARMInstrThumb.td
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll
test/CodeGen/ARM/atomic-ops-v8.ll
test/CodeGen/ARM/debug-frame-vararg.ll
test/CodeGen/ARM/frame-register.ll
test/CodeGen/ARM/thumb1-varalloc.ll
test/CodeGen/ARM/thumb1_return_sequence.ll
test/CodeGen/Thumb/stack-access.ll [new file with mode: 0644]
test/CodeGen/Thumb/stm-merge.ll
test/CodeGen/Thumb/vargs.ll