[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0

[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0

Summary:
GCC compresses the pseudo instruction "mv rd, rs",  which is an alias of
"addi rd, rs, 0", to "c.mv rd, rs".

In LLVM we rely on the canonical MC instruction (MCInst) to do our compression
checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv
rd, rs" we lose this compression opportunity to gcc.

 In this patch we fix that by adding an addi to c.mv compression pattern, the
 instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like
 gcc does.

Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal).

Reviewers: asb, apazos, zzheng, mgrang, shiva0217

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits

Differential Revision: https://reviews.llvm.org/D45583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329939 91177308-0d34-0410-b5e6-96231b3b80d8